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| author | Craig Topper <craig.topper@sifive.com> | 2021-03-25 23:29:34 -0700 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2021-03-25 23:31:01 -0700 |
| commit | 8f62a80328e34aee34246af4d7e3981ebe9ef37f (patch) | |
| tree | 6b225519c300bc36b40b90fb91bcc945f91d4984 /llvm/lib/Bitcode/Reader/BitcodeReader.cpp | |
| parent | 5a18c576c45cba4d90a492e3162e547e04f060df (diff) | |
[RISCV] Optimize (and (shl GPR:, uimm5:), 0xffffffff) to use 2 shifts instead of 3.
The and would normally become SLLI+SRLI, giving us 2 SLLI+SRLI. We
can detect this and combine the 2 SLLIs into 1.
Diffstat (limited to 'llvm/lib/Bitcode/Reader/BitcodeReader.cpp')
0 files changed, 0 insertions, 0 deletions