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| author | Craig Topper <craig.topper@sifive.com> | 2022-03-21 14:27:09 -0700 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2022-03-21 14:50:55 -0700 |
| commit | 8c4937b33fe9090546f6dc834e174177075b5084 (patch) | |
| tree | a107ed2f035714c1f888ae5bdc214bc52d3580c5 /llvm/lib/Bitcode/Reader/BitcodeReader.cpp | |
| parent | b40f420c2b64ff902ddf16fba1d9920acad11fbc (diff) | |
[RISCV] Special case sign extended scalars when type legalizing nxvXi64 .vx instrinsics on RV32.
On RV32, we need to type legalize i64 scalar arguments to intrinsics.
We usually do this by splatting the value into a vector separately.
If the scalar happens to be sign extended, we can continue using a .vx
intrinsic.
We already special cased sign extended constants, this extends it
to any sign extended value.
I've only added tests for one case of vadd. Most intrinsics go
through the same check. I can add more tests if we're concerned.
Differential Revision: https://reviews.llvm.org/D122186
Diffstat (limited to 'llvm/lib/Bitcode/Reader/BitcodeReader.cpp')
0 files changed, 0 insertions, 0 deletions