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| author | Shengchen Kan <shengchen.kan@intel.com> | 2023-11-24 12:29:56 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-11-24 12:29:56 +0800 |
| commit | 8c2537fde66406dd08021d28e302e1cdb862fc3f (patch) | |
| tree | 14364168d20184b1f520b6dbd1d321b0a4cdbff8 /llvm/lib/Bitcode/Reader/BitcodeReader.cpp | |
| parent | be0307d5769f87a2e64b7e9e78a78bcd3dcca800 (diff) | |
[X86][MC] Support encoding/decoding for PUSH2[P]/POP2[P] (#73233)
PUSH2 and POP2 are two new instructions for (respectively)
pushing/popping 2 GPRs at a time to/from
the stack. The opcodes of PUSH2 and POP2 are those of “PUSH r/m” and
“POP r/m” from legacy map 0, but we
require ModRM.Mod = 3 in order to disallow memory operand.
The 1-bit Push-Pop Acceleration hint described in #73092 applies to
PUSH2/POP2 too, then we have PUSH2P/POP2P.
For AT&T syntax, PUSH2[P] pushes the registers from right to left onto
the stack. POP2[P] pops the stack to registers from right to left. Intel
syntax has the opposite order - from left to right.
The assembly syntax is aligned with GCC & binutils
https://gcc.gnu.org/pipermail/gcc-patches/2023-November/637718.html
Diffstat (limited to 'llvm/lib/Bitcode/Reader/BitcodeReader.cpp')
0 files changed, 0 insertions, 0 deletions