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authorSameer Sahasrabuddhe <sameer.sahasrabuddhe@amd.com>2024-05-06 14:07:11 +0530
committerGitHub <noreply@github.com>2024-05-06 14:07:11 +0530
commit8a65ee8b2a05e276ab64682c3c9d3f93490cedcc (patch)
treef678fb9f0cedddd276c556e5b0ac50da209a727d /llvm/lib/Bitcode/Reader/BitcodeReader.cpp
parentd3dad7a74be50d90754bf5c072e1a2330e92712c (diff)
[AMDGPU] don't mark control-flow intrinsics as convergent (#90026)
This is really a workaround to allow control flow lowering in the presence of convergence control tokens. Control-flow intrinsics in LLVM IR are convergent because they indirectly represent the wave CFG, i.e., sets of threads that are "converged" or "execute in lock-step". But they exist during a small window in the lowering process, inserted after the structurizer and then translated to equivalent MIR pseudos. So rather than create convergence tokens for these builtins, we simply mark them as not convergent. The corresponding MIR pseudos are marked as having side effects, which is sufficient to prevent optimizations without having to mark them as convergent.
Diffstat (limited to 'llvm/lib/Bitcode/Reader/BitcodeReader.cpp')
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