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| author | Sudharsan Veeravalli <quic_svs@quicinc.com> | 2025-07-21 12:03:55 +0530 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-07-21 12:03:55 +0530 |
| commit | 84e689b1db02be1687c3093d66ace913250780bd (patch) | |
| tree | e41aae0d633bc295239d69cdc957a487506b51c3 /llvm/lib/Bitcode/Reader/BitcodeReader.cpp | |
| parent | 3813567e08e202280546dd9fd5ae891d067cbda9 (diff) | |
[RISCV] Swap source register operands in QC_SHLADD ISEL patterns (#149697)
The instruction does `rd = (rs1 << shamt) + rs2` but the ISEL patterns
had `rs1` and `rs2` the other way around which is incorrect.
Diffstat (limited to 'llvm/lib/Bitcode/Reader/BitcodeReader.cpp')
0 files changed, 0 insertions, 0 deletions