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| author | chendewen <chendewen3@huawei.com> | 2023-01-17 09:47:35 +0800 |
|---|---|---|
| committer | zhongyunde <zhongyunde@huawei.com> | 2023-01-17 09:56:31 +0800 |
| commit | 6ef6b2b5162ef48a63fb2697d77cffa6d7b1f7e7 (patch) | |
| tree | 2fe978a30b07444bd794b51ceae2f5a55cbe0ec6 /llvm/lib/Bitcode/Reader/BitcodeReader.cpp | |
| parent | 59bc64c667f3e1fb724a4180ed2e6c78857d918e (diff) | |
[AArch64][SVE] Add more intrinsics in 'isZeroingInactiveLanes'.
The REINTERPRET_CAST operation generates redundant and and ptrue instructions.
For some instructions, this is redundant, because its inactive lanes are zeroed by construction.
For example. Codegen before:
```
facgt p2.d, p0/z, z4.d, z1.d
ptrue p1.d
and p1.b, p2/z, p2.b, p1.b
```
After:
```
facgt p1.d, p0/z, z4.d, z1.d
```
ref: https://reviews.llvm.org/D129851
Reviewed By:sdesmalen
Differential Revision:https://reviews.llvm.org/D141469
Diffstat (limited to 'llvm/lib/Bitcode/Reader/BitcodeReader.cpp')
0 files changed, 0 insertions, 0 deletions