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| author | Emmmer <yjhdandan@163.com> | 2022-12-10 16:59:13 +0800 |
|---|---|---|
| committer | Emmmer <yjhdandan@163.com> | 2022-12-16 00:58:26 +0800 |
| commit | 6493fc4bccd2a5365f3f3a4f205acb8c1409bd0d (patch) | |
| tree | bb06d0bec2b1da93a0e473e3358e19dc9c872996 /llvm/lib/Bitcode/Reader/BitcodeReader.cpp | |
| parent | 38f1abef860418f85b1011601d20e9d49aa85adb (diff) | |
[LLDB][RISCV] Add RVD instruction support for EmulateInstructionRISCV
RVD extension is a double-precision floating-point instruction-set extension, which adds double-precision floating-point computational instructions compliant with the IEEE 754-2008 arithmetic standard.
This patch:
- Reuse most of the functions in the "F extension" to impl the"D extension"
- corresponding unittests.
Reviewed By: DavidSpickett
Differential Revision: https://reviews.llvm.org/D140032
Diffstat (limited to 'llvm/lib/Bitcode/Reader/BitcodeReader.cpp')
0 files changed, 0 insertions, 0 deletions