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| author | Craig Topper <craig.topper@sifive.com> | 2021-03-27 15:33:39 -0700 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2021-03-27 15:37:18 -0700 |
| commit | 5692fc38e0d17abc55a4a84da98f021a1d53d76d (patch) | |
| tree | 7ce1accce0f10389e1e031d039d3a64f75083294 /llvm/lib/Bitcode/Reader/BitcodeReader.cpp | |
| parent | 9075864b7375b4eb8f2c0663caa575c0c667de7c (diff) | |
[RISCV] Add a pattern for (sext_inreg (mul (and X, 0xffffffff), (and Y, 0xffffffff)), i32) to suppress MULW formation
We have a special pattern for
(mul (and X, 0xffffffff), (and Y, 0xffffffff)), to optimize the
ANDs to shift. But if a sext_inreg coms first, we'll form a MULW
and limit the effectiveness of the special match. So this patch
adds a larger pattern to suppress the MULW formation by emitting
a sext.w and then the same output we use for the
(mul (and X, 0xffffffff), (and Y, 0xffffffff)). This should all
get CSEd.
This is the issue I was trying to fix with D99029, but that affected
many more tests.
Diffstat (limited to 'llvm/lib/Bitcode/Reader/BitcodeReader.cpp')
0 files changed, 0 insertions, 0 deletions