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| author | Sanjay Patel <spatel@rotateright.com> | 2021-11-05 09:25:54 -0400 |
|---|---|---|
| committer | Sanjay Patel <spatel@rotateright.com> | 2021-11-05 10:06:16 -0400 |
| commit | 4fc1fc4005f7818e1f8a795ca15ca8f8c03e426a (patch) | |
| tree | 3f62409c9c4afe126cda11e2af3929da261b5304 /llvm/lib/Bitcode/Reader/BitcodeReader.cpp | |
| parent | 1e7afa2a0dd76af177f23695c69892764f33534e (diff) | |
[DAGCombiner] add fold for vselect based on mask of signbit
(X s< 0) ? Y : 0 --> (X s>> BW-1) & Y
We canonicalize to the icmp+select form in IR, and we already have this fold
for scalar select in SDAG, so I think it's an oversight that we don't have
the fold for vectors. It seems neutral for AArch64 and saves some instructions
on x86.
Whether we should also have the sibling folds for the inverse condition or
all-ones true value may depend on target-specific factors such as whether
there's an "and-not" instruction.
Differential Revision: https://reviews.llvm.org/D113212
Diffstat (limited to 'llvm/lib/Bitcode/Reader/BitcodeReader.cpp')
0 files changed, 0 insertions, 0 deletions