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authorAhmed Bougacha <ahmed.bougacha@gmail.com>2016-12-21 23:26:20 +0000
committerAhmed Bougacha <ahmed.bougacha@gmail.com>2016-12-21 23:26:20 +0000
commit36f7035bd7d0e99abfc362da20894388c2515605 (patch)
treea640aa3559a78de0475e100ec63089300a18ec06 /llvm/lib/Bitcode/Reader/BitcodeReader.cpp
parentaa9fe53278677f6f80a4b05476da47d06bf1e584 (diff)
[GlobalISel] Add basic Selector-emitter tblgen backend.
This adds a basic tablegen backend that analyzes the SelectionDAG patterns to find simple ones that are eligible for GlobalISel-emission. That's similar to FastISel, with one notable difference: we're not fed ISD opcodes, so we need to map the SDNode operators to generic opcodes. That's done using GINodeEquiv in TargetGlobalISel.td. Otherwise, this is mostly boilerplate, and lots of filtering of any kind of "complicated" pattern. On AArch64, this is sufficient to match G_ADD up to s64 (to ADDWrr/ADDXrr) and G_BR (to B). Differential Revision: https://reviews.llvm.org/D26878 llvm-svn: 290284
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