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| author | Craig Topper <craig.topper@sifive.com> | 2022-12-07 12:25:30 -0800 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2022-12-07 12:25:30 -0800 |
| commit | 258bb453fb84b2f149a51adf9ebfd535f4288fe2 (patch) | |
| tree | d2102fc19132f0cd16900d8a4fe6477d16495aa3 /llvm/lib/Bitcode/Reader/BitcodeReader.cpp | |
| parent | 92e54b09ce076a9e5e109d52e4fff6b1530dcb7a (diff) | |
[RISCV] Without Zfh, promote f16 inputs before creating RISCVISD::FCVT_W(U)_RV64 nodes.
This allows us to remove a couple more Zfhmin isel patterns.
Diffstat (limited to 'llvm/lib/Bitcode/Reader/BitcodeReader.cpp')
0 files changed, 0 insertions, 0 deletions