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| author | Craig Topper <craig.topper@sifive.com> | 2021-02-22 09:39:56 -0800 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2021-02-22 09:53:46 -0800 |
| commit | 1aeb927fedbeee328913ba085bb8860fbafaa1b1 (patch) | |
| tree | 241119ee84adca18570fbfc3bb081b2e84515505 /llvm/lib/Bitcode/Reader/BitcodeReader.cpp | |
| parent | 15332982c3d8d1c9e8bd7ae9f76f22f77adb51ee (diff) | |
[RISCV] Custom isel the rest of the vector load/store intrinsics.
A previous patch moved the index versions. This moves the rest.
I also removed the custom lowering for VLEFF since we can now
do everything directly in the isel handling.
I had to update getLMUL to handle mask registers to index the
pseudo table correctly for VLE1/VSE1.
This is good for another 15K reduction in llc size.
Reviewed By: frasercrmck
Differential Revision: https://reviews.llvm.org/D97097
Diffstat (limited to 'llvm/lib/Bitcode/Reader/BitcodeReader.cpp')
0 files changed, 0 insertions, 0 deletions