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| author | Fraser Cormack <fraser@codeplay.com> | 2021-05-17 11:13:19 +0100 |
|---|---|---|
| committer | Fraser Cormack <fraser@codeplay.com> | 2021-05-18 09:21:25 +0100 |
| commit | 175bdf127d5bb09c81fbd3dc1e766e4ef26793d0 (patch) | |
| tree | 550befb6af3d68121af1993b97124ad1643c4919 /llvm/lib/Bitcode/Reader/BitcodeReader.cpp | |
| parent | cc1a6361d34e270b407f91a6e2e76c7fb324ee2d (diff) | |
[RISCV] Fix operand order in fixed-length VM(OR|AND)NOT patterns
Where the RVV specification writes `vs2, vs1`, our TableGen patterns use
`rs1, rs2`. These differences can easily cause confusion. The VMANDNOT
instruction performs `LHS && !RHS`, and similarly for VMORNOT.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D102606
Diffstat (limited to 'llvm/lib/Bitcode/Reader/BitcodeReader.cpp')
0 files changed, 0 insertions, 0 deletions