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authorJameson Nash <vtjnash@gmail.com>2025-06-11 21:49:01 -0400
committerGitHub <noreply@github.com>2025-06-11 21:49:01 -0400
commit082251bba4effea7f60191c6cbddacb3705c07db (patch)
treedff60797f07b93c2f82ec61c8b3cc24dc37c0dc1 /llvm/lib/Bitcode/Reader/BitcodeReader.cpp
parent52360d195b85608c677d781272534dfa61e9a1c3 (diff)
[AArch64] fix trampoline implementation: use X15 (#126743)
AAPCS64 reserves any of X9-X15 for a compiler to choose to use for this purpose, and says not to use X16 or X18 like GCC (and the previous implementation) chose to use. The X18 register may need to get used by the kernel in some circumstances, as specified by the platform ABI, so it is generally an unwise choice. Simply choosing a different register fixes the problem of this being broken on any platform that actually follows the platform ABI (which is all of them except EABI, if I am reading this linux kernel bug correctly https://lkml2.uits.iu.edu/hypermail/linux/kernel/2001.2/01502.html). As a side benefit, also generate slightly better code and avoids needing the compiler-rt to be present. I did that by following the XCore implementation instead of PPC (although in hindsight, following the RISCV might have been slightly more readable). That X18 is wrong to use for this purpose has been known for many years (e.g. https://www.mail-archive.com/gcc@gcc.gnu.org/msg76934.html) and also known that fixing this to use one of the correct registers is not an ABI break, since this only appears inside of a translation unit. Some of the other temporary registers (e.g. X9) are already reserved inside llvm for internal use as a generic temporary register in the prologue before saving registers, while X15 was already used in rare cases as a scratch register in the prologue as well, so I felt that seemed the most logical choice to choose here.
Diffstat (limited to 'llvm/lib/Bitcode/Reader/BitcodeReader.cpp')
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