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authorBaptiste Saleil <baptiste.saleil@ibm.com>2020-09-28 14:12:14 -0500
committerBaptiste Saleil <baptiste.saleil@ibm.com>2020-09-28 14:39:37 -0500
commit0156914275be5b07155ecefe4dc2d58588265abc (patch)
tree39cb0945172e7ca7d8de15dece7e64ddd9a45c0d /llvm/lib/Bitcode/Reader/BitcodeReader.cpp
parent33125cffda96fd5c5d2b80eebfa89fbf4f6b76a6 (diff)
[PowerPC] Legalize v256i1 and v512i1 and implement load and store of these types
This patch legalizes the v256i1 and v512i1 types that will be used for MMA. It implements loads and stores of these types. v256i1 is a pair of VSX registers, so for this type, we load/store the two underlying registers. v512i1 is used for MMA accumulators. So in addition to loading and storing the 4 associated VSX registers, we generate instructions to prime (copy the VSX registers to the accumulator) after loading and unprime (copy the accumulator back to the VSX registers) before storing. This patch also adds the UACC register class that is necessary to implement the loads and stores. This class represents accumulator in their unprimed form and allow the distinction between primed and unprimed accumulators to avoid invalid copies of the VSX registers associated with primed accumulators. Differential Revision: https://reviews.llvm.org/D84968
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