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| author | Craig Topper <craig.topper@sifive.com> | 2022-06-09 15:48:21 -0700 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2022-06-09 16:07:35 -0700 |
| commit | 8bbcb988481c4b072e5f545ef222078ff2a8df3b (patch) | |
| tree | 8ee3f5440d12a37b8f1ea9f882964e32ce3a52f7 /lldb/test/API/python_api | |
| parent | f1182bd6d538847acac58316e794f5b60bc3c89a (diff) | |
[RISCV] Teach RISCVMergeBaseOffset about cases where we use SHXADD to add some immediates.
For an addition with simm14 and simm15 immediates with 2 or 3 trailing bits,
we can use a shXadd instruction and an addi to do the addition.
This patch teaches RISCVMergeBaseOffset to see through this pattern.
I don't think the sh1add case occurs because we use two addis for that,
but I implemented it for completeness.
Reviewed By: reames
Differential Revision: https://reviews.llvm.org/D127376
Diffstat (limited to 'lldb/test/API/python_api')
0 files changed, 0 insertions, 0 deletions