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| author | Craig Topper <craig.topper@sifive.com> | 2023-05-30 14:38:16 -0700 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2023-05-30 14:38:16 -0700 |
| commit | 463f50b436a2ac3000a90d273f2ed05893e8864f (patch) | |
| tree | f176127416ed09d92bcdb81c56119bb66f07826c /lldb/test/API/python_api/process/main.cpp | |
| parent | 6b4b63a832f105039442fc983d0b309abe5261d5 (diff) | |
[RISCV] Add RISCVISD::VFWMUL_VL. Use it to replace isel patterns with a DAG combine.
This is more consistent with how we handle integer widening multiply.
A follow up patch will add support for matching vfwmul when the
multiplicand is being squared.
Diffstat (limited to 'lldb/test/API/python_api/process/main.cpp')
0 files changed, 0 insertions, 0 deletions