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| author | Vladislav Dzhidzhoev <vdzhidzhoev@accesssoftek.com> | 2023-02-07 17:48:58 +0100 |
|---|---|---|
| committer | Vladislav Dzhidzhoev <vdzhidzhoev@accesssoftek.com> | 2023-02-07 21:33:44 +0100 |
| commit | 90c98f8e5516901cd5dbd677e65fb8d7dd483cba (patch) | |
| tree | 0864151d57db524b6a5f3b47d5c6cc4c966366e1 /lldb/test/API/python_api/process/TestProcessAPI.py | |
| parent | 836249b1c2f0540ed0c886d6c3558b2f4f179249 (diff) | |
[AArch64][GlobalISel] Legalize wide s8/s16 vectors G_ADD/G_MUL/G_OR/...
Clamp the max number of elements of s8/s16 vectors when legalizing G_ADD,
G_SUB, G_MUL, G_AND, G_OR, G_XOR, in order to support some wide vectors.
Fixes https://github.com/llvm/llvm-project/issues/58156.
Differential Revision: https://reviews.llvm.org/D143517
Diffstat (limited to 'lldb/test/API/python_api/process/TestProcessAPI.py')
0 files changed, 0 insertions, 0 deletions