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| author | Mirko Brkusanin <Mirko.Brkusanin@rt-rk.com> | 2020-02-11 11:35:23 +0100 |
|---|---|---|
| committer | Mirko Brkusanin <Mirko.Brkusanin@rt-rk.com> | 2020-02-11 11:47:30 +0100 |
| commit | 5ba931a84a3466aebab5d6dde3525e7a27c40c28 (patch) | |
| tree | a0b6c6afd20a7c91bc397ab36a54432b2c8d767d /lldb/test/API/python_api/module_section/TestModuleAndSection.py | |
| parent | cb0c4ee3ebfe55809c9d0be72726b05668028fc4 (diff) | |
[Mips] Add intrinsics for 4-byte and 8-byte MSA loads/stores.
New intrinisics are implemented for when we need to port SIMD code from other
arhitectures and only load or store portions of MSA registers.
Following intriniscs are added which only load/store element 0 of a vector:
v4i32 __builtin_msa_ldrq_w (const void *, imm_n2048_2044);
v2i64 __builtin_msa_ldr_d (const void *, imm_n4096_4088);
void __builtin_msa_strq_w (v4i32, void *, imm_n2048_2044);
void __builtin_msa_str_d (v2i64, void *, imm_n4096_4088);
Differential Revision: https://reviews.llvm.org/D73644
Diffstat (limited to 'lldb/test/API/python_api/module_section/TestModuleAndSection.py')
0 files changed, 0 insertions, 0 deletions