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| author | Chenyang Gao <cygao09@gmail.com> | 2023-12-20 16:43:18 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-12-20 16:43:18 +0800 |
| commit | f72b65499156171eca25ad0e7becb274347c7c02 (patch) | |
| tree | db29bb0a694745f33e0a1456cff7246126279eff /lldb/test/API/python_api/global_module_cache/TestGlobalModuleCache.py | |
| parent | bbe6c81f808093c4030d7904136ff2f9dad6e73b (diff) | |
[MC][x86] Allow non-MCTargetExpr RHS when the LHS of a MCBinaryExpr is MCTargetExpr (#75693)
This fixes #73109.
In instruction `addl %eax %rax`, because there is a missing comma in the
middle of two registers, the asm parser will treat it as a binary
expression.
```
%rax % rax --> register mod identifier
```
However, In `MCExpr::evaluateAsRelocatableImpl`, it only checks the left
side of the expression. This patch ensures the right side will also be
checked.
Diffstat (limited to 'lldb/test/API/python_api/global_module_cache/TestGlobalModuleCache.py')
0 files changed, 0 insertions, 0 deletions