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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2025-05-27 23:34:47 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-05-27 23:34:47 +0200 |
| commit | d79312b28c5c1c9cfddbd1de80a8bd942e2cbff4 (patch) | |
| tree | 5c1770a144a8ca189525044e1ee76961d535fa3e /lldb/test/API/python_api/global_module_cache/TestGlobalModuleCache.py | |
| parent | 777163ca99edd23deb5bedfd8b941cb46c96500d (diff) | |
RISCV: Remove faulty assert that ignored subregister uses (#141658)
This was asserting the raw virtual register class was a scalar
class, instead of computing the net result of the register class
plus the subregister index on the operand. The machine verifier
should be checking this was a valid combination in the first place,
so just drop the assert.
Diffstat (limited to 'lldb/test/API/python_api/global_module_cache/TestGlobalModuleCache.py')
0 files changed, 0 insertions, 0 deletions