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| author | Christudasan Devadasan <christudasan.devadasan@amd.com> | 2024-10-08 15:13:12 +0530 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-10-08 15:13:12 +0530 |
| commit | 6636f32615000429f6391b68392e826c1de1ed64 (patch) | |
| tree | c084acbf65b1958857b3fd38b4940e35830f0f6e /lldb/test/API/python_api/global_module_cache/TestGlobalModuleCache.py | |
| parent | 39cdfdfad961e146131966757d563bfd667246d6 (diff) | |
[AMDGPU] Include WWM register spill into BB Prolog (#111496)
With #93526 we split the regalloc pipeline further
to have a standalone allocation for wwm registers
and per-lane VGPRs. Currently the presence of the
wwm-spill reloads inserted at the bb-top limits the
isBasicPrologue function during the per-lane vgpr
regalloc to skip past the exec manipulation instruction
and ended up causing incorrect codegen. The wmm-spill
inserted during the wwm-regalloc pipeline should also
be included in the bb-prolog so that the per-lane vgpr
regalloc pipeline can identify the appropriate insertion
points for their spills and copies.
Diffstat (limited to 'lldb/test/API/python_api/global_module_cache/TestGlobalModuleCache.py')
0 files changed, 0 insertions, 0 deletions