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| author | Craig Topper <craig.topper@sifive.com> | 2023-12-19 15:07:38 -0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-12-19 15:07:38 -0800 |
| commit | 05abe8a7e8b466c656b8461e2c01338cf4eb82db (patch) | |
| tree | 1c94f9b3739c1200c4a7ba896f30b183768b4a8f /lldb/test/API/python_api/global_module_cache/TestGlobalModuleCache.py | |
| parent | 8ddf98ad4bb14867987b48a37dd29750c665112f (diff) | |
[RISCV] Remove Zfbfmin dependency from Zvfbfmin. (#75851)
Zvfbfmin does not have any scalar operands making this an unnecessary
dependency. The spec was just updated to remove this. See
https://github.com/riscv/riscv-bfloat16/commit/86d7a74f4b928e981f79f6d84a4592e6e9e4c0e9
This fixes a correctness issue where Xsfvfwmaccqqq was incorrectly
depending on Zfbfmin. The SiFive CPUs that support Xsfvfwmaccqqq do not
implement Zfbfmin, but do implement Zvfbfmin based on a previous
understanding that it only requires Zve32f. I've added tests for this
feature to raise the bar for adding dependencies to it in the future.
Diffstat (limited to 'lldb/test/API/python_api/global_module_cache/TestGlobalModuleCache.py')
0 files changed, 0 insertions, 0 deletions
