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| author | Min-Yih Hsu <min.hsu@sifive.com> | 2024-05-30 08:47:27 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-05-30 08:47:27 -0700 |
| commit | 6147a7b5f9479a4163c07064a9c78c2d5fe40d27 (patch) | |
| tree | 42aa9fd4f59ee03ef4f6fe81c9ff9d47c81e1556 /lldb/test/API/python_api/debugger/TestDebuggerAPI.py | |
| parent | a2bcb932f3130c3c18ceb06872da9002f6845c4b (diff) | |
[RISCV] Adjust FP load latencies from 6 to 5 in SiFiveP400/P600 scheduling models (#93735)
According to our performance measurements, FLH/W/D have load latencies
closer to 5 rather than 6 in these two models.
Diffstat (limited to 'lldb/test/API/python_api/debugger/TestDebuggerAPI.py')
0 files changed, 0 insertions, 0 deletions