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| author | Craig Topper <craig.topper@sifive.com> | 2022-02-09 08:05:42 -0800 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2022-02-09 08:10:21 -0800 |
| commit | e305b1de7ebdc6b7f701cae01e6d2615357cda5a (patch) | |
| tree | 976a40dfc0896e46dd2530c8e47860c82de35cf6 /lldb/test/API/functionalities/scripted_process/TestStackCoreScriptedProcess.py | |
| parent | d9d2ebbfcb201dc09150d514766ceb669b254a28 (diff) | |
[RISCV] Pre-process integer ISD::SPLAT_VECTOR to RISCISD::VMV_V_X_VL before isel.
This allows us to remove some isel patterns that exist for both
operations. Saving nearly 3000 bytes from the isel table.
Reviewed By: frasercrmck
Differential Revision: https://reviews.llvm.org/D119197
Diffstat (limited to 'lldb/test/API/functionalities/scripted_process/TestStackCoreScriptedProcess.py')
0 files changed, 0 insertions, 0 deletions