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| author | Craig Topper <craig.topper@sifive.com> | 2022-02-09 12:03:22 -0800 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2022-02-09 12:33:01 -0800 |
| commit | c45c1b130b5cdb16426f5f7758a8518ea449ff69 (patch) | |
| tree | b1125f69f396e87b62f2e1f64a4cf52593158b0b /lldb/test/API/functionalities/scripted_process/TestStackCoreScriptedProcess.py | |
| parent | 0ed0a8e2f045fb69cee002d1c358641a9cee22ad (diff) | |
[RISCV] Teach RISCVDAGToDAGISel::selectShiftMask to replace sub from constant with neg.
If the shift amount is (sub C, X) where C is 0 modulo the size of
the shift, we can replace it with neg or negw.
Similar is is done for AArch64 and X86.
Reviewed By: khchen
Differential Revision: https://reviews.llvm.org/D119089
Diffstat (limited to 'lldb/test/API/functionalities/scripted_process/TestStackCoreScriptedProcess.py')
0 files changed, 0 insertions, 0 deletions