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| author | Craig Topper <craig.topper@sifive.com> | 2023-06-21 08:57:46 -0700 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2023-06-21 08:57:46 -0700 |
| commit | aae155c50b07cf2358d72055457c133f4a71e1eb (patch) | |
| tree | 1cd7936580cc1d08c8b347b23b9ee7e369b343ac /lldb/test/API/functionalities/scripted_process/TestStackCoreScriptedProcess.py | |
| parent | 7e334ac0ec6c58ad44a24a033a869b2b0c50742d (diff) | |
[RISCV] Use a build_vector instead of a chain insert_vector_elts for vXi1 build_vector lowreing.
A build_vector is the canonical representation rather than multiple
insert_vector_elts.
Unfortunately, this regresses quite a few tests now primarily due to not
having a vmv.s.x special case, but I hope we can improve this with future
patches.
Stress testing in our downstream found an infinite loop in DAG combine.
This patch breaks the infinite loop.
The insert_vector_element chain starts with a fixed vector undef.
Fixed vector undef is currently expanded to a build_vector of 0s
which gets lowered to a vmv.v.i. The insert chain overwrites all
elements so SimplifyDemandedVectorElts turns the vmv.v.i back into
undef and the cycle repeats.
We probably should custom lower fixed vector undef to scalable
vector undef. I think that would also fix the infinite loop, but
I didn't test that.
Reviewed By: luke
Differential Revision: https://reviews.llvm.org/D153399
Diffstat (limited to 'lldb/test/API/functionalities/scripted_process/TestStackCoreScriptedProcess.py')
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