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| author | Craig Topper <craig.topper@sifive.com> | 2022-04-07 16:10:30 -0700 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2022-04-08 09:04:04 -0700 |
| commit | 1903b9915456e06c46e3014f8cc41f4471de28a0 (patch) | |
| tree | 331880cb360a5708315d931dde155655343eb3e1 /lldb/test/API/functionalities/scripted_process/TestStackCoreScriptedProcess.py | |
| parent | 57f4dcfe154fb55eebab3039ab9e4b62ab959a31 (diff) | |
[RISCV] Always select (and (srl X, C), Mask) as (srli (slli X, C2), C3).
SLLI is always compressible to C.SLLI as long as the source and dest
register is the same.
ANDI and SRLI are only compressible if the register is x8-x15. By
using SLLI we have a better chance of generating shorter code.
I had to exclude one exclusion for the BEXTI case so that it's
pattern match could still fire.
Reviewed By: luismarques
Differential Revision: https://reviews.llvm.org/D123336
Diffstat (limited to 'lldb/test/API/functionalities/scripted_process/TestStackCoreScriptedProcess.py')
0 files changed, 0 insertions, 0 deletions