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authorCraig Topper <craig.topper@sifive.com>2020-11-04 11:01:52 -0800
committerCraig Topper <craig.topper@sifive.com>2020-11-04 11:13:25 -0800
commitd47300f503c90511304e4999182060b8e1e86b0f (patch)
treefc2d9df044a39a2c9e018361466153a0661a2d38 /lldb/test/API/functionalities/plugins/python_os_plugin/TestPythonOSPlugin.py
parent77a9e0a4af5aea3795ed79a0db61ee5b19b837e4 (diff)
[RISCV] Correct the operand order for fshl/fshr to fsl/fsr instructions.
fsl/fsr take their shift amount in $rs2 or an immediate. The sources are $rs1 and $rs3. fshl/fshr ISD opcodes both concatenate operand 0 in the high bits and operand 1 in the lower bits. fshl returns the high bits after shifting and fshr returns the low bits. So a shift amount of 0 returns operand 0 for fshl and operand 1 for fshr. fsl/fsr concatenate their operands in different orders such that $rs1 will be returned for a shift amount of 0. So $rs1 needs to come from operand 0 of fshl and operand 1 of fshr. Differential Revision: https://reviews.llvm.org/D90735
Diffstat (limited to 'lldb/test/API/functionalities/plugins/python_os_plugin/TestPythonOSPlugin.py')
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