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| author | Benjamin Maxwell <benjamin.maxwell@arm.com> | 2024-02-16 11:34:34 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-02-16 11:34:34 +0000 |
| commit | 7dcca6213258bf2df2dd8a7d555c9a12c1484759 (patch) | |
| tree | 407961fb155d96c4d7af4bd233a2bc7a0815bfca /lldb/test/API/functionalities/plugins/python_os_plugin/TestPythonOSPlugin.py | |
| parent | f06e07be9a41978e39fdf22f6174194cf8382047 (diff) | |
[mlir][ArmSVE] Add `arm_sve.zip.x2` and `arm_sve.zip.x4` ops (#81278)
This adds ops for the two and four-way SME 2 multi-vector zips.
See:
-
https://developer.arm.com/documentation/ddi0602/2023-12/SME-Instructions/ZIP--two-registers---Interleave-elements-from-two-vectors-?lang=en
-
https://developer.arm.com/documentation/ddi0602/2023-12/SME-Instructions/ZIP--four-registers---Interleave-elements-from-four-vectors-?lang=en
Diffstat (limited to 'lldb/test/API/functionalities/plugins/python_os_plugin/TestPythonOSPlugin.py')
0 files changed, 0 insertions, 0 deletions