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| author | Craig Topper <craig.topper@sifive.com> | 2022-06-16 15:05:59 -0700 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2022-06-16 15:11:03 -0700 |
| commit | 5afdceb82b9296ab95ff57c54913354e74a0da02 (patch) | |
| tree | b53e6a263cc6d43743e6bb0bafc17d31a6321b01 /lldb/test/API/functionalities/plugins/python_os_plugin/TestPythonOSPlugin.py | |
| parent | ee28837a1fbd574dbec14b9f09cb4effab6a492a (diff) | |
[RISCV] Add RISCVISD opcode for PseudoLLA.
Rather than emitting a MachineSDNode from lowering. Let isel match it.
This is consistent with the RISCVISD::HI and ADD_LO nodes that were
also added. Having them both the same will make D127679 consistent.
Reviewed By: reames
Differential Revision: https://reviews.llvm.org/D127714
Diffstat (limited to 'lldb/test/API/functionalities/plugins/python_os_plugin/TestPythonOSPlugin.py')
0 files changed, 0 insertions, 0 deletions