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| author | Craig Topper <craig.topper@sifive.com> | 2020-11-04 10:35:05 -0800 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2020-11-04 10:35:05 -0800 |
| commit | 0122a4ea661db4c2509143a4035c8857eedd9aa5 (patch) | |
| tree | ced56ba5ac5370fea8575f3c6e4848cf6ebb8e69 /lldb/test/API/functionalities/plugins/python_os_plugin/TestPythonOSPlugin.py | |
| parent | 8c2025cc617aa0413dee269084b4a66bcb7de4d5 (diff) | |
[RISCV] Remove assertsexti32 from inputs to riscv_sllw/srlw nodes in B extension isel patterns.
riscv_sllw/srlw only reads the lower 32 bits of the first operand.
And the lower 5 bits of the second operands. Whether the upper
32 bits of the input are sign bits or not doesn't matter.
Also use ineg and not to shorten the patterns.
Differential Revision: https://reviews.llvm.org/D90668
Diffstat (limited to 'lldb/test/API/functionalities/plugins/python_os_plugin/TestPythonOSPlugin.py')
0 files changed, 0 insertions, 0 deletions