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| author | Craig Topper <craig.topper@sifive.com> | 2021-12-28 18:28:23 -0800 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2021-12-28 18:55:36 -0800 |
| commit | f7b096d754d6424f825d7e08af04b7ade985c77b (patch) | |
| tree | b678b770610e028f4987a69b3ce12a3720e58a0b /lldb/test/API/functionalities/module_cache/simple_exe/TestModuleCacheSimple.py | |
| parent | dd2fbbbb2d277a5dd497edbd01b1fcd469e65f53 (diff) | |
[RISCV] Add more div by constant test cases.
Some constants require more instructions than others. This adds
additional test for each variation. UDIV has 2 variations, SDIV has
4 variations.
Some of these sequence may have gotten worse on RV32 when we started
doing the div by constant optimization before type legalization. We
materialized a smaller constant, but we require more instructions
to emulate 8 or 16 bit right shifts. This was hidden by the lack
of test coverage.
I've also added Zba and Zbb test cases to show the affect of sext.b,
sext.h, zext.h, and zext.w on some of the shifts. In some cases
we end up generating more code after the multiply because we use
a zext.h+srli and sext.h+srai where without Zbb we share a slli
between a srli and srai.
Diffstat (limited to 'lldb/test/API/functionalities/module_cache/simple_exe/TestModuleCacheSimple.py')
0 files changed, 0 insertions, 0 deletions