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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2021-12-16 16:46:39 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2021-12-16 16:54:27 +0000 |
| commit | a640f16ca2da46bb5fcd522d2130234a41e157e9 (patch) | |
| tree | 3dc3332e4a3e5d69372014636c83e42e91befa21 /lldb/test/API/functionalities/module_cache/simple_exe/TestModuleCacheSimple.py | |
| parent | 333d66b09494b7ebc1a89f2befa79128a56f77e3 (diff) | |
[X86] combineAnd - don't demand operand vector elements if the other operand element is zero
If either operand has a zero element, then we don't need the equivalent element from the other operand, as no bits will be set.
Diffstat (limited to 'lldb/test/API/functionalities/module_cache/simple_exe/TestModuleCacheSimple.py')
0 files changed, 0 insertions, 0 deletions