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| author | Craig Topper <craig.topper@sifive.com> | 2023-05-26 09:01:28 -0700 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2023-05-26 09:06:38 -0700 |
| commit | c5e6c886aabb36ab66b4ed835da243c2a3455ade (patch) | |
| tree | b60da4c9c196b204ae89af3b34e77a2e04fa6e08 /lldb/test/API/functionalities/interactive_scripted_process/TestInteractiveScriptedProcess.py | |
| parent | bfb1ba752655bf09b35c486f6cc9817dbedfb1bb (diff) | |
[VP][SelectionDAG][RISCV] Add get_vector_length intrinsics and generic SelectionDAG support.
The generic implementation is umin(TC, VF * vscale).
Lowering to vsetvli for RISC-V will come in a future patch.
This patch is a pre-requisite to be able to CodeGen vectorized code from
D99750.
Reviewed By: reames, frasercrmck
Differential Revision: https://reviews.llvm.org/D149916
Diffstat (limited to 'lldb/test/API/functionalities/interactive_scripted_process/TestInteractiveScriptedProcess.py')
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