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| author | Craig Topper <craig.topper@sifive.com> | 2022-01-06 08:24:32 -0800 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2022-01-06 08:27:27 -0800 |
| commit | ec4dd862bf548c157b2c992efe4f10da4f04c4e2 (patch) | |
| tree | 58e43da0dd15b24679344de9adc6dde99afce1bc /lldb/source/Plugins/ScriptInterpreter/Python | |
| parent | e3a261831bd98bb4dc54bb861a196a7540c4747a (diff) | |
[RISCV] Use simm5_plus1_nonzero in isel patterns for vmsgeu.vi/vmsltu.vi intrinsics.
The 0 immediate can't be selected to vmsgtu.vi/vmsleu.vi by decrementing
the immediate. To prevent his we had special patterns that provided
alternate lowering for the 0 cases. This relied on tablegen prioritizing
the 0 pattern over the sim5_plus1 range.
This patch introduces simm5_plus1_nonzero that excludes 0. It also
excludes the special case for vmsltu.vi since we can just use
vmsltu.vx and let the 0 be selected to X0.
This is an alternative to some of the changes in D116584.
Reviewed By: Chenbing.Zheng, asb
Differential Revision: https://reviews.llvm.org/D116723
Diffstat (limited to 'lldb/source/Plugins/ScriptInterpreter/Python')
0 files changed, 0 insertions, 0 deletions