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| author | Matt Devereau <matthew.devereau@arm.com> | 2022-07-12 15:54:53 +0000 |
|---|---|---|
| committer | Matt Devereau <matthew.devereau@arm.com> | 2022-07-21 10:56:43 +0000 |
| commit | e0fbd990c9cb367a3820fc788d18d9859d9380fc (patch) | |
| tree | 068cd0a83ce932df964c80f208fa2265f88bff4f /lldb/source/Plugins/ScriptInterpreter/Python/ScriptedThreadPythonInterface.cpp | |
| parent | 2feb99b02c886201c9774f4f24df14299105b321 (diff) | |
[AArch64][SVE] Add ISel pattern to lower DUPLANE128 to LD1RQD
Following on from https://reviews.llvm.org/D128902, lower DUPLANE128 to LD1RQD
for integer load types from instruction selection.
Differential Revision: https://reviews.llvm.org/D130010
Diffstat (limited to 'lldb/source/Plugins/ScriptInterpreter/Python/ScriptedThreadPythonInterface.cpp')
0 files changed, 0 insertions, 0 deletions