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| author | Craig Topper <craig.topper@sifive.com> | 2022-07-20 22:18:25 -0700 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2022-07-20 22:32:11 -0700 |
| commit | add17fc8e4ceb78fb7eafac49d519001c168bd7a (patch) | |
| tree | 775a66b1048e34f642f229249428bbe402cba9b3 /lldb/source/Plugins/ScriptInterpreter/Python/ScriptedProcessPythonInterface.cpp | |
| parent | 28800c2e18972935cd4f942aa428c5e6cc4c1670 (diff) | |
[RISCV] Combine (select_cc (srl (and X, 1<<C), C), 0, eq/ne, true, fale)
(srl (and X, 1<<C), C) is the form we receive for testing bit C.
An earlier combine removed the setcc so it wasn't there to match
when we created the SELECT_CC. This doesn't happen for BR_CC because
generic DAG combine rebuilds the setcc if it is used by BRCOND.
We can shift X left by XLen-1-C to put the bit to be tested in the
MSB, and use a signed compare with 0 to test the MSB.
Diffstat (limited to 'lldb/source/Plugins/ScriptInterpreter/Python/ScriptedProcessPythonInterface.cpp')
0 files changed, 0 insertions, 0 deletions