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| author | Valery Pykhtin <Valery.Pykhtin@amd.com> | 2016-04-07 13:41:51 +0000 |
|---|---|---|
| committer | Valery Pykhtin <Valery.Pykhtin@amd.com> | 2016-04-07 13:41:51 +0000 |
| commit | e23b6deb01e0e68734814ad48ab6de4980a8cd6b (patch) | |
| tree | a0953e7b666b7426a3cc473b3b00556de54c4f8e /lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp | |
| parent | af16b958c0a0746f3b3fc354443a6b16ff83a7ee (diff) | |
[AMDGPU] fix readlane/readfirstlane src vgpr operand type.
For VGPR_32 operand disassembler expects a VGPR register encoded as 0..255 (enum8 src operand).
readfirstlane/readline actually has enum9 operand and this change fixes VGPR_32 to VS_32 (enum9 encoding).
Differential Revision: http://reviews.llvm.org/D18696
llvm-svn: 265670
Diffstat (limited to 'lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp')
0 files changed, 0 insertions, 0 deletions