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authorJonas Paulsson <paulsson@linux.vnet.ibm.com>2020-09-08 13:06:41 +0200
committerJonas Paulsson <paulsson@linux.vnet.ibm.com>2020-10-13 15:09:52 +0200
commitc78da037783bda0f27f4d82060149166e6f0c796 (patch)
treea5224c2a449f34a9c58d095aaaab2e046cb4dae0 /lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp
parentdfc72439529c49e8bfeab9d604b1aa1cac7d89e8 (diff)
[clang] Improve handling of physical registers in inline assembly operands.
Change EmitAsmStmt() to - Not tie physregs with the "+r" constraint, but instead add the hard register as an input constraint. This makes "+r" and "=r":"r" look the same in the output. Background: Macro intensive user code may contain inline assembly statements with multiple operands constrained to the same physreg. Such a case (with the operand constraints "+r" : "r") currently triggers the TwoAddressInstructionPass assertion against any extra use of a tied register. Furthermore, TwoAddress will insert a COPY to that physreg even though isel has already done so (for the non-tied use), which may lead to a second redundant instruction currently. A simple fix for this is to not emit tied physreg uses in the first place for the "+r" constraint, which is what this patch does. - Give an error on multiple outputs to the same physical register. This should be reported and this is also what GCC does. Review: Ulrich Weigand, Aaron Ballman, Jennifer Yu, Craig Topper Differential Revision: https://reviews.llvm.org/D87279
Diffstat (limited to 'lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp')
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