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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2019-03-24 16:30:35 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2019-03-24 16:30:35 +0000 |
| commit | a71c0ed471eb06e2879d8687b427dcf6333474c3 (patch) | |
| tree | 687a03d9a3c4fa413cc8a33d642badac2ad943c3 /lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp | |
| parent | 4dc851964c03c37d4c8dc635fc92e34c0ae0eb2f (diff) | |
[X86][AVX] Start shuffle combining from ZERO_EXTEND_VECTOR_INREG (PR40685)
Just enable this for AVX for now as SSE41 introduces extra register moves for the PMOVZX(PSHUFD(V)) -> UNPCKH(V,0) pattern (but otherwise helps reduce port5 usage on Intel targets).
Only AVX support is required for PR40685 as the issue is due to 8i8->8i32 zext shuffle leftovers.
llvm-svn: 356858
Diffstat (limited to 'lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp')
0 files changed, 0 insertions, 0 deletions