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| author | Simon Tatham <simon.tatham@arm.com> | 2022-01-20 13:22:34 +0000 |
|---|---|---|
| committer | Simon Tatham <simon.tatham@arm.com> | 2022-01-20 13:37:58 +0000 |
| commit | a4ac40e92f718d487898bd204517c38113afd3bb (patch) | |
| tree | 9a7beed55c369c2b5c75c17030cb30b8b2d0da0d /lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp | |
| parent | 19b9cd4eae6fd84ff380c9769052522658c950fc (diff) | |
[AArch64] Remove PRBAR0_ELn and PRLAR0_ELn sysregs.
The Armv8-R.64 architecture defines numbered MPU region registers with
indices 1-15, not 0-15. So there's no such register as PRBAR0_EL2 or
PRLAR0_EL1 (for example). The encodings that they would occupy are
used for the unnumbered PRBAR_ELn and PRLAR_ELn registers.
Reviewed By: labrinea
Differential Revision: https://reviews.llvm.org/D117755
Diffstat (limited to 'lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp')
0 files changed, 0 insertions, 0 deletions