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| author | Simon Pilgrim <llvm-dev@redking.me.uk> | 2020-01-14 11:20:09 +0000 |
|---|---|---|
| committer | Simon Pilgrim <llvm-dev@redking.me.uk> | 2020-01-14 11:41:47 +0000 |
| commit | a43b0065c5c78eba3fb83881fb628f5b8182db64 (patch) | |
| tree | 983d795963a172cda345f34ac75d1b66d6a29190 /lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp | |
| parent | e73b20c57dc7a8c847ebadeb7e19c08ec84f5bd7 (diff) | |
[SelectionDAG] ComputeKnownBits - merge getValidMinimumShiftAmountConstant() and generic ISD::SRL handling.
As mentioned by @nikic on rGef5debac4302 (although that was just about SHL), we can merge the guaranteed top zero bits from the shifted value, and then, if a min shift amount is known, zero out the top bits as well.
SHL tests / handling will be added in a follow up patch.
Diffstat (limited to 'lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp')
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