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authorVenkata Ramanaiah Nalamothu <quic_vnalamot@quicinc.com>2025-01-28 21:03:12 +0530
committerGitHub <noreply@github.com>2025-01-28 21:03:12 +0530
commita0b049055df592759e4ac1d8032139f385581c63 (patch)
tree8df8570bbe8bf713511fb4398da77bffe3e37b5a /lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp
parent2abde54aabc4b8878a5665e4d70a0525e9041456 (diff)
[RISC-V] Fix incorrect epilogue_begin setting in debug line table (#120623)
The DwarfDebug.cpp implementation expects the epilogue instructions to have source location of last non-debug instruction after which the epilogue instructions are inserted. The epilogue_begin is set on location of the first FrameDestroy instruction with source line information that has been seen in the epilogue basic block. In the trunk, the risc-v backend sets the epilogue_begin after the epilogue has actually begun i.e. after callee saved register reloads and the source line information is not set on those reload instructions. This is leading to #120553 where, while debugging, breaking on or single stepping to the epilogue_begin location will make accessing the variables from wrong place as the FP has been restored to the parent frame's FP. To fix that, this patch sets FrameSetup/FrameDestroy flags on the callee saved register spill/reload instructions which is actually correct. Then the RISCVInstrInfo::loadRegFromStackSlot uses FrameDestroy flag to identify a reload of the callee saved register in the epilogue and copies the source line information from insert position instruction to that reload instruction. Requires PR #120622 Fixes #120553
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