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| author | Sergey Kozub <skozub@nvidia.com> | 2024-08-19 19:34:22 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-08-19 10:34:22 -0700 |
| commit | 865952bbbb97655410d2c34c21938134059c4076 (patch) | |
| tree | 7b8d7cc4f52c99898cf0bad12fbb39a24fc9e61e /lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp | |
| parent | 7f968e3aea41264a952692a4bf32e5e2b612d44e (diff) | |
[NVPTX] Add conversion intrinsics from/to fp8 types (e4m3, e5m2) (#102969)
PTX ISA 8.1 supports FP8 conversions:
https://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-cvt
This PR adds the support for:
- cvt.rn.satfinite{.relu}.f8x2type.f32 d, a, b;
- cvt.rn.satfinite{.relu}.f8x2type.f16x2 d, a;
- cvt.rn.{.relu}.f16x2.f8x2type d, a;
where .f8x2type = { .e4m3x2, .e5m2x2 };
Diffstat (limited to 'lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp')
0 files changed, 0 insertions, 0 deletions