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authorCraig Topper <craig.topper@sifive.com>2024-06-25 15:55:09 -0700
committerGitHub <noreply@github.com>2024-06-25 15:55:09 -0700
commit847235bbef153c6d805d415cea8494297eaf2bdb (patch)
treed445fa6e315c9d505feea6184cceb2006133ba6e /lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp
parente214ed9d7060f6caa0c1bb756edb62643f23aa5b (diff)
[RISCV] Add DAG combine to turn (sub (shl X, 8), X) into orc.b (#96680)
If only bits 8, 16, 24, 32, etc. can be non-zero. This is what (mul X, 255) is decomposed to. This decomposition happens early before RISC-V DAG combine runs. This patch does not support types larger than XLen so i64 on rv32 fails to generate 2 orc.b instructions. It might have worked if the mul hadn't been decomposed before it was expanded. Partial fix for #96595.
Diffstat (limited to 'lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp')
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