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| author | Lukacma <Marian.Lukac@arm.com> | 2024-05-23 14:36:58 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-05-23 14:36:58 +0100 |
| commit | 7a1022a3895f51a3c11dd326c47d861575ffaf55 (patch) | |
| tree | 7b28f0e1c13d354f4d0af9b1265267d4dcc00492 /lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp | |
| parent | 05c154f2bcba34f002b1f0c22c7a9e9614e9d83c (diff) | |
[AArch64][SME] Add intrinsics for vector groups ZERO (#88114)
According to the specification in
https://github.com/ARM-software/acle/pull/309 this adds the intrinsics:
```
void svzero_za64_vg1x2(uint32_t slice)
__arm_streaming __arm_inout("za");
void svzero_za64_vg1x4(uint32_t slice)
__arm_streaming __arm_inout("za");
void svzero_za64_vg2x1(uint32_t slice)
__arm_streaming __arm_inout("za");
void svzero_za64_vg2x2(uint32_t slice)
__arm_streaming __arm_inout("za");
void svzero_za64_vg2x4(uint32_t slice)
__arm_streaming __arm_inout("za");
void svzero_za64_vg4x1(uint32_t slice)
__arm_streaming __arm_inout("za");
void svzero_za64_vg4x2(uint32_t slice)
__arm_streaming __arm_inout("za");
void svzero_za64_vg4x4(uint32_t slice)
__arm_streaming __arm_inout("za");
```
Diffstat (limited to 'lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp')
0 files changed, 0 insertions, 0 deletions