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| author | Craig Topper <craig.topper@sifive.com> | 2021-02-18 09:01:51 -0800 |
|---|---|---|
| committer | Craig Topper <craig.topper@sifive.com> | 2021-02-18 09:08:10 -0800 |
| commit | 792627be359e5d3386c4d8bb97eb1e5e5ec43b0c (patch) | |
| tree | d6ed874bf6ce992b67801f6e4d3d2d713f7a4e82 /lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp | |
| parent | c7dd92e8a590cd456b4daad87af9d3b746d05ca6 (diff) | |
[RISCV] Add support for fixed vector sign/zero extend from mask types.
Due to vXi64 on RV32, I've directly emitted this using _VL ISD
opcodes. If it wasn't for that we could just use fixed vector
BUILD_VECTOR and VSELECT and let those each be legalized.
Reviewed By: frasercrmck
Differential Revision: https://reviews.llvm.org/D96910
Diffstat (limited to 'lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp')
0 files changed, 0 insertions, 0 deletions