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| author | hassnaaHamdi <hassnaa.hamdi@arm.com> | 2023-10-26 16:09:59 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-10-26 16:09:59 +0100 |
| commit | 78941e1eedb121344e0d969458ea85598cd749df (patch) | |
| tree | 53bb4b2f2c4b08a2e8e0471fae12e93a52348492 /lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp | |
| parent | 2d0ac85b6693eb6e25b4120c0e4e224c42a84462 (diff) | |
[llvm][AArch64][Assembly]: Add FP8 instructions assembly and disassembly. (#69632)
This patch adds the feature flag FP8 and the assembly/disassembly
for the following instructions of NEON, SVE2 and SME2:
* NEON Instructions:
+ Advanced SIMD two-register miscellaneous:
- F1CVTL, F1CVTL2, F2CVTL, F2CVTL2
- BF1CVTL, BF1CVTL2, BF2CVTL, BF2CVTL2
+ Advanced SIMD three-register extension:
- FCVTN, FCVTN2 (FP32 to FP8)
- FCVTN (FP16 to FP8)
+ Advanced SIMD three same:
- FSCALE
* SVE2 Instructions:
+ Downconvert instructions:
- FCVTN_Z2Z_HtoB
- FCVTNB_Z2Z_StoB
- BFCVTN_Z2Z_HtoB
- FCVTNT_Z2Z_StoB
+ Upconvert instructions:
- F1CVT_ZZ, F2CVT_ZZ
- BF1CVT_ZZ, BF2CVT_ZZ
- F1CVTLT_ZZ, F2CVTLT_ZZ
- BF1CVTLT_ZZ, BF2CVTLT_ZZ
* SME2 Instructions:
- F1CVT_2ZZ, F2CVT_2ZZ
- BF1CVT_2ZZ, BF2CVT_2ZZ
- F1CVTL_2ZZ, F2CVTL_2ZZ
- BF1CVTL_2ZZ, BF2CVTL_2ZZ
- FCVT_Z2Z_HtoB, BFCVT_Z2Z_HtoB
- FCVT_Z4Z - FCVTN_Z4Z
- FSCALE_2ZZ, FSCALE_4ZZ
- FSCALE_2Z2Z, FSCALE_4Z4Z
That is according to this documentation:
https://developer.arm.com/documentation/ddi0602/2023-09
Diffstat (limited to 'lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp')
0 files changed, 0 insertions, 0 deletions