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| author | Hsiangkai Wang <kai.wang@sifive.com> | 2021-09-23 07:48:46 +0800 |
|---|---|---|
| committer | Hsiangkai Wang <kai.wang@sifive.com> | 2021-10-28 13:34:53 +0800 |
| commit | 7051f73d696ebfcbb160104b9f925c8a98e557c7 (patch) | |
| tree | b9112af1a4c5754d338815fce71de0c86bbb326a /lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp | |
| parent | 130055647922ffa9dd9abd5a838727773f73c48a (diff) | |
[RISCV] Sync Zvlsseg register order as the same as vector registers.
Sync the order of Zvlsseg registers with vector registers to avoid
unnecessary register copies between vector instructions and zvlsseg
instructions.
Differential Revision: https://reviews.llvm.org/D110250
Diffstat (limited to 'lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp')
0 files changed, 0 insertions, 0 deletions